From the birth of the first integrated circuits in 1960, the number of devices on each chip has increased at an explosive rate. The progress of the semiconductor integrated circuits has led to an ULSI (ultra large scale integration) or even higher level after four decades of development. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Integrated circuit devices such as transistors, capacitors, and connections must be greatly narrowed accommodate these advancements.
However with the narrowing of feature sizes, a great number of challenges arise at the same time. The narrowed spaces between a lot of structures or individual devices are hard to be filled by subsequently formed layers. The unfilled spaces lead to the problems of hollow defects. In some cases, the layer covered over the hollow spaces might reflow in a later process and cause undesired topographical problems.
Without limiting the scope of the present invention, an example of a polyimide layer over conductive structures is illustrated as the background of the invention. The recess problems can be found with the formation of a subsequent layer over a non-planar surface and other various cases are not described in detail.
Turning to FIG. 1A, a top view of a portion of a semiconductor substrate with structures formed over is illustrated. Conductive structures M1 and M2 are formed thereon and the figure is shown with a portion of the conductive structure layout at a comer or turn-around region. A cross-sectional view along line B-B' is shown in FIG. 1B. In general, a passivation layer 12 is formed over the conductive structures to act as conductive path passivations. With the narrow space 14 between the conductive structures M1 and M2, the two mushroom passivation film merge to form an unopened hole in-between.
Referring to FIG. 1C, a cross-sectional view along line C-C' in FIG. 1A is shown. At the corner region where conductive structures M1 and M2 turn around, the width 16 between M1 and M2 is wider than the width of the space 14 between the two straight paths. Therefore, an unfilled and top-opened space 18 is left after the formation of the passivation layer 12.
Typically, a buffer layer 20 is formed over a last layer of the interconnection layers, namely the layer with conductive structures M1 and M2, as shown in FIG. 2. The buffer layer is used as a protection layer over the whole chip to reduce the stress-induced damage or cracks in the chip-packaging process. In general, organic polymer materials like polyimide are used as the buffer layer 20. With only a small top opening in the narrow space 18, a subsequently formed buffer layer 20 is hard to fill in and the space 18 is left unfilled.
However with a later thermal process like a soft-bake process, the buffer layer is heated and reflow can occur. The space 18 might be filled and a recess region 22 is formed on the top surface of the buffer layer 20, as shown in FIG. 3. The undesired formation of the recess region 22 can be observed by an optical microscope inspection step. In the inspection with a top view of the substrate, the recess region 22 observed is a dark region or a black point, as shown in FIG. 4.
Typically, the recess region on the surface of the buffer layer is caused by material redistribution in the reflow process. Thus, a plurality of recess regions can be present on a wafer at regions such as the turn-around regions of the conductive structures, or the end-point of the conductive structures.
In inspection processes such as ADI (after development inspection), AEI (after etching inspection), etc., the presentation of dark regions or black points are usually mis-identified as defects and cause the substrate to be identified as defective. The wrongly identified substrate or wafer is sent to a rework process. Thus the yield of the process is greatly damaged and unnecessary inspection efforts and rework process efforts are increased.
What is needed is a method to form a planar and recess-free layer, especially on a non-planar surface with island structures.